2017 ASEE Annual Conference & Exposition

An introductory computer engineering course where students learn about combinational and sequential circuits is fundamental to any Electrical and Computer Engineering (ECE) curriculum. Many of these courses are taught using a hardware description language (HDL) such as Verilog or VHDL. However, younger students traditionally struggle with HDLs due to their abstract nature. The students are used to designing with traditional logic gates and structures, but are often confused by the software-like interface that an HDL provides. This creates a disconnection between the student's experience in the classroom where the students learn with one method (visually with gates and structures) and in labs or projects where they are asked to implement designs using text descriptors. Often times a student's frustration with HDLs leads to them being disinterested in digital systems or even computer engineering as a major. This paper will describe the transition of an introductory Computer Engineering course from primarily using Verilog for its lab assignments to instead using a combination of schematic capture (which is very similar to what they see in class) and Verilog. With this course's redesign, the author saw the student's self-reported confidence in their design skills improve by 44% (from 41% to 85%) and their interest in taking additional computer engineering courses improve by 10% (from 66% to 76%).